In digital system applications, progressively more sophisticated architectures are required to meet the higher performance goals of every new generation of digital systems. As the operating frequencies of these systems increase, timing delays in components such as flip-flops need to be reduced. Delays introduced by flip-flops such as clock-to-Q time (the time between a data capture clock transition and a stable output), setup time (the amount of time a data signal must be stable prior a clock capturing transition), and hold time (the amount of time the data signal must be stable after the clock rising edge), etc. contribute to lower circuit operating frequencies.